1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to an improved and novel manufacturing process and device configuration for providing the power device with flexible Crss adjustment to smooth the waveforms and to avoid electromagnetic interference (EMI) in the shield gate trench (SGT) MOSFET for enhanced DC-DC applications.
2. Description of the Prior Art
Conventional technologies for designing and manufacturing power devices for DC-DC application are still confronted with a difficulty due to a reduced voltage peak of the phase node particularly for DC-DC devices of higher efficiency that requires the voltage peak of phase node to be lower than 80% drain-to-source voltage (VDS) rating to avoid the electromagnetic interference (EMI). These technical issues often limit and adversely affect the device performance.
Furthermore, conventional technologies for reducing the gate to drain capacitance Cgd in a power semiconductor device by implementing the shielded gate trench (SGT) configuration are still confronted with other technical limitations and difficulties. Specifically, the source electrode disposed on the trench bottom in the conventional SGT devices are connected to the source voltage through an edge area of the semiconductor power device. This inevitably increases the source electrode resistance. Furthermore, the extra masks needed to create such connection also increase the cost of manufacturing. Many patented inventions have disclosed such configurations.
Baliga discloses in U.S. Pat. No. 5,998,833 a DMOS cell as shown in FIG. 1A. A source electrode is placed underneath the trenched gate to reduce the gate-to-drain capacitance. The gate of the DMOS cell is divided into two segments. The gate-to-drain capacitance is reduced because the contributions to capacitance from the gate-drain overlapping areas are eliminated.
In U.S. Pat. No. 6,690,062, a MOSFET device as shown in FIG. 1B is disclosed where the switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. There is a capacitance between an edge gate structure and a drain zone. The shielding electrode located in the edge region reduces the capacitance between an edge gate structure and a drain zone hence reduces the gate-drain capacitance CGD of the transistor.
In U.S. Pat. No. 6,891,223, Krumrey et al. disclose a transistor that includes transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches. Furthermore, metallization structures are disposed above the substrate surface as shown in FIG. 1C. The trenches extend into an inactive edge region of the transistor. An electrical connection between the electrode structures and corresponding metallization are established in the edge regions.
However, the above patented-disclosures including transistor configurations still have the common difficulty that the source electrode disposed on the trench bottom in the conventional SGT devices are connected to the source voltage through an edge area of the semiconductor power device. As there are growing demands for high frequency switch power devices, an urgent need exists to provide effective solutions to achieve the purpose of resolving these technical difficulties and limitations. For power transistors including MOSFET and IGBT, a new device configuration and manufacturing process are necessary to reduce the speed-limiting capacitance between the gate and the drain of these switching power devices.
Additionally, there is a need to improve on the conventional configuration by connecting the shielding electrode underneath the top gate segment to the source to satisfy the reduced voltage peak requirement of the phase node and to avoid the EMI issues in the power devices for the DC-DC applications.
Therefore, there is a need in the art of power semiconductor device design and manufacture to provide new manufacturing method and device configuration in forming the power devices such that the above discussed problems and limitations can be resolved.